Conventional CMOS technology has reached the brink of its scaling limits and poses significant challenges for the development of next generation high-speed, low-power, cost-effective memory, and processing devices. In the post-CMOS era, “Spintronics” could emerge as a potentially viable interdisciplinary field with credible technological perspectives. This technology exploits an electron’s spin orientation and its associated magnetic moment as a state variable instead of a conventionally used charge in CMOS technology. In general, spintronic devices are layered structures of magnetic materials that provide the non-volatile storage options and manipulations of logic states. Spin transfer torque (STT) and spin orbit torque (SOT) devices using magnetic tunnel junctions (MTJs) have become strong contenders for the non-volatile embedded memory architectures with the capability of implementing the concepts of “logic-in-memory” and “material-device-circuit co-design”. The spin torque devices offer the features of “universal memory”, i.e. high-speed, nonvolatility, high density, and low-power, high-endurance and CMOS process compatibility. The memory density is in ever increasing demand due to complex functionalities and storage requirements. This talk presents the operation principle and performance comparison of spintronics based single-bit STT and SOT magnetic RAM (MRAM), dual-level cells (DLCs), three-level cells (TLCs), and four-level cells (FLCs). It is observed that the multilevel MRAM technology is far more efficient in terms of static power consumption and area overhead, respectively as compared to the available SRAMs. This talk will also discuss in-memory computing circuits using multi-level cells.
Speaker(s): Brajesh Kumar Kaushik,